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2011
IWLS
 N. Een, A. Mishchenko, and R. Brayton, "Efficient Implementation of Property Directed Reachability". Proc. IWLS'11. PDF PPTX
2010
FMCAD
 N. Een, A. Mishchenko, and N. Amla, "A SingleInstance Incremental SAT Formulation of Proof and CounterexampleBased Abstraction". Proc. FMCAD'10. PDF
IWLS
 S. Ray, A. Mishchenko, and R. Brayton, "Synthesisguided partial hierarchy collapsing". Submitted to IWLS'10. PDF
 A. Kennings, A. Mishchenko, K. Vorwerk, V. Pevzner, and A. Kundu, "Generating efficient libraries for use in FPGA resynthesis algorithms". Submitted to IWLS'10. PDF
 H. Savoj, D. Berthelot, A. Mishchenko, and R. Brayton, "Combinational techniques for sequential equivalence checking". Submitted to IWLS'10. PDF
 S. Ray, A. Mishchenko, R. K. Brayton, S. Jang, and T. Daniel, "Minimumperturbation retiming for delay optimization". Submitted to IWLS'10. PDF
 A. Mishchenko, N. Een, R. K. Brayton, S. Jang, M. Ciesielski, and T. Daniel, "Magic: An industrialstrength logic optimization, technology mapping, and formal verification tool". Submitted to IWLS'10. PDF
DATE
 D. Strukov and A. Mishchenko, "Monolithically stackable hybrid FPGA", Proc. DATE'10.
FPGA
 A. Mishchenko, R. Brayton, and S. Jang, "Global delay optimization using structural choices", Proc. FPGA'10, pp. 181184. PDF
Journals
 J.H. R. Jiang, C.C. Lee, A. Mishchenko, and C.Y. R. Huang, "To SAT or not to SAT: Scalable exploration of functional dependency", IEEE Trans. Computers. To appear.
 A. Mishchenko, R. Brayton, J.H. R. Jiang, and S. Jang. "Scalable don'tcarebased logic optimization and resynthesis", ACM Trans. Reconfigurable Technology and Systems (TRETS). Submitted.
 K.H. Chang, V. Bertacco, I. L. Markov, and A. Mishchenko, "Logic synthesis and circuit customization using extensive external don'tcares", ACM TODAES. To appear.
2009
Journals
 S. Jang, B. Chan, K. Chung, and A. Mishchenko, "WireMap: FPGA technology mapping for improved routability and enhanced LUT merging". ACM Trans. Reconfigurable Technology and Systems (TRETS), Vol. 2(2), June 2009, Article 14. PDF
IWLS
 S. Jang, K. Chung, A. Mishchenko, and R. Brayton, "A power optimization toolbox for logic synthesis and mapping", Proc. IWLS'09, pp. 18. PDF
 S. Ray, A. Mishchenko, and R. Brayton, "Incremental sequential equivalence checking and subgraph isomorphism", Proc. IWLS'09, pp. 3742. PDF
 T. Sasao and A. Mishchenko, "LUTMIN: FPGA logic synthesis with MUXbased and cascade realizations", Proc. IWLS'09, pp. 310316. PDF
DATE
 H. Mony, J. Baumgartner, A. Mishchenko, and R. Brayton, "Speculative reductionbased scalable redundancy identification", Proc. DATE'09. PDF

V. Kravets and A. Mishchenko, "Sequential logic synthesis using
symbolic bidecomposition", Proc. DATE'09.
PDF
FPGA
 S. Jang, D. Wu, M. Jarvin, B. Chan, K. Chung, A. Mishchenko, and R. Brayton, "SmartOpt: An industrial strength framework for logic synthesis", Proc. FPGA'09, pp. 237240. PDF
 A. Mishchenko, R. Brayton, J.H. R. Jiang, and S. Jang, "Scalable don't care based logic optimization and resynthesis", Proc. FPGA'09, pp. 151160. PDF
Technical reports
 A. Mishchenko, R. Brayton, and S. Jang, "Global delay optimization using structural choices", ERL Technical Report, EECS Dept., UC Berkeley, 2009. PDF
2008
FMCAD
 M. L. Case, A. Mishchenko, R. K. Brayton, J. Baumgartner, and H. Mony, "Invariantstrengthened elimination of dependent state elements", Proc. FMCAD'08, pp. 917. PDF
 A. Mishchenko and R. K. Brayton, "Recording synthesis history for sequential verification", Proc. FMCAD'08, pp. 2734. PDF
ICCAD
 A. Mishchenko, M. L. Case, R. K. Brayton, and S. Jang, "Scalable and scalablyverifiable sequential synthesis", Proc. ICCAD'08, pp. 234241. PDF
 A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks", Proc. ICCAD'08, pp. 3844. PDF
IWLS
 A. Mishchenko, R. K. Brayton, and S. Jang, "Global delay optimization using structural choices", Proc. IWLS'08, pp. 16. PDF
 A. Mishchenko, M. L. Case, R. K. Brayton, and S. Jang, "Scalable and scalablyverifiable sequential synthesis", Proc. IWLS'08, pp. 110117. (See ICCAD'08.)
 A. Mishchenko and R. K. Brayton, "Recording synthesis history for sequential verification", Proc. IWLS'08, pp. 240246. PDF
 A. Mishchenko, R. K. Brayton, and S. Chatterjee, "Boolean factoring and decomposition of logic networks", Proc. IWLS'08, pp. 145151. (See ICCAD'08.)
 M. L. Case, A. Mishchenko, and R. K. Brayton, "Cutbased inductive invariant computation", Proc. IWLS'08, pp. 253258. PDF
 K.H. Chang, V. Bertacco, I. L. Markov, and A. Mishchenko, "Synthesis with external don'tcares using Shannon entropy and Craig interpolation", Proc. IWLS'08, pp. 165172. PDF
DAC
 A. P. Hurst, A. Mishchenko, and R. K. Brayton, "Scalable minarea retiming under simultaneous delay and initial state constraints". Proc. DAC'08, pp. 534539. PDF
 M. L. Case, V. N. Kravets, A. Mishchenko, and R. K. Brayton, "Merging nodes under sequential observability", Proc. DAC'08, pp. 540545. PDF
FPGA
 S. Jang, B. Chan, K. Chung, and A. Mishchenko, "WireMap: FGPA technology mapping for improved routability". Proc. FPGA '08, pp. 4755. PDF
Technical reports
 M. L. Case, S. A. Seshia, A. Mishchenko, and R. K. Brayton, "Conflict guided simplication for SAT". ERL Technical Report, EECS Dept., UC Berkeley. 2008. PDF (Experimental results reported in this paper contain a performance bug.)
2007
ICCAD
 A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. ICCAD '07, pp. 354361. PDF
 C.C. Lee, J.H. R. Jiang, C.Y. Huang, and A. Mishchenko. "Scalable exploration of functional dependency by interpolation and incremental SAT solving", Proc. ICCAD '07, pp. 227233. PDF
FMCAD
 M. L. Case, A. Mishchenko, and R. K. Brayton, "Automated extraction of inductive invariants to aid model checking", Proc. FMCAD '07, pp. 165172. PDF
 A. Hurst, A. Mishchenko, and R. Brayton, "Fast minimumregister retiming via binary maximumflow", Proc. FMCAD '07, pp. 181187. PDF
DAC
 S. Chatterjee, A. Mishchenko, R. Brayton, and A. Kuehlmann, "On resolution proofs for combinational equivalence". Proc. DAC '07, pp. 600605. PDF
IWLS
 R. Brayton and A. Mishchenko, "Sequential rewriting", Proc. IWLS '07, pp. 18. PDF
 A. Hurst, A. Mishchenko, and R. Brayton, "Minimizing implementation costs with endtoend retiming", Proc. IWLS '07, pp. 916. PDF
 A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Combinational and sequential mapping with priority cuts", Proc. IWLS '07, pp. 9198. (See ICCAD'07.)
 J. Pistorius, M. Hutton, A. Mishchenko, and R. Brayton. "Benchmarking method and designs targeting logic synthesis for FPGAs", Proc. IWLS '07, pp. 230237. PDF
 M. L. Case, A. Mishchenko, and R. K. Brayton, "Automated extraction of inductive invariants to aid model checking", Proc. IWLS '07, pp. 282289. (See FMCAD'07.)
 A. Hurst, A. Mishchenko, and R. Brayton, "Fast minimumregister retiming via binary maximumflow", Proc. IWLS '07, pp. 328335. (See FMCAD'07.)
 S. Chatterjee, Z. Wei, A. Mishchenko, and R. Brayton, "A linear time algorithm for optimum tree placement", Proc. IWLS '07, pp. 336342. PDF
 A. Mishchenko, R. Brayton, J.H. R. Jiang, and S. Jang, "SATbased logic optimization and resynthesis", Proc. IWLS '07, pp. 358364. PDF
 C.C. Lee, J.H. R. Jiang, C.Y. Huang, and A. Mishchenko. "Scalable exploration of functional dependency by interpolation and incremental SAT solving", Proc. IWLS '07, pp. 365371. (See ICCAD'07.)
SAT
 N. Een, A. Mishchenko, and N. Sorensson, "Applying logic synthesis to speedup SAT", Proc. SAT '07, pp. 272286. PDF
FPGA
 S. Cho, S. Chatterjee, A. Mishchenko, and R. Brayton, "Efficient FPGA mapping using priority cuts". (Poster.) Proc. FPGA '07. PDF
Technical reports
 A. Mishchenko, S. Chatterjee, and R. Brayton, "Fast Boolean matching for LUT structures". ERL Technical Report, EECS Dept., UC Berkeley, 2007. PDF
 A. Mishchenko, R. Brayton, J.H. R. Jiang, and S. Jang, "SATbased logic optimization and resynthesis". ERL Technical Report, EECS Dept., UC Berkeley, 2007. PDF
 R. Brayton and A. Mishchenko, "Scalablyverifiable sequential synthesis", ERL Technical Report, EECS Dept., UC Berkeley, 2007. PDF
 R. Brayton and A. Mishchenko, "Scalable sequential verification", ERL Technical Report, EECS Dept., UC Berkeley, 2007. PDF
 A. Hurst, A. Mishchenko, and R. Brayton, "Fast minimumregister retiming via binary maximumflow", ERL Technical Report, EECS Dept., UC Berkeley, 2007. PDF
 A. Mishchenko, S. Cho, S. Chatterjee, and R. Brayton, "Cutless FPGA mapping", ERL Technical Report, EECS Dept., UC Berkeley, 2007. PDF
2006
Journals
 A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for LUTbased FPGAs". IEEE TCAD, Vol. 26(2), Feb 2007, pp. 240253. PDF
ICCAD
 S. Chatterjee, A. Mishchenko, and R. Brayton, "Factor cuts", Proc. ICCAD '06, pp. 143150. PDF
 A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een, "Improvements to combinational equivalence checking", Proc. ICCAD '06, pp. 836843. PDF
DAC
 J. S. Zhang, A. Mishchenko, R. Brayton, and M. ChrzanowskaJeske, "Symmetry detection for large boolean functions using circuit representation, simulation, and satisfiability", Proc. DAC '06, pp. 510515. PDF
 A. Mishchenko, S. Chatterjee, and R. Brayton, "DAGaware AIG rewriting: A fresh look at combinational logic synthesis", Proc. DAC '06, pp. 532536. PDF
IWLS
 S. Chatterjee, A. Mishchenko, and R. Brayton, "Factor cuts", Proc. IWLS '06, pp. 18. (See ICCAD'06)
 M. L.Case, A. Mishchenko, and R. K. Brayton, "Inductively finding a reachable state space overapproximation", Proc. IWLS '06, pp. 172179. PDF
 A. Mishchenko, S. Chatterjee, R. Brayton, and N. Een, "Improvements to combinational equivalence checking", Proc. IWLS '06, pp. 180187. (See ICCAD'06)
 A. Mishchenko and R. K. Brayton, "Scalable logic synthesis using a simple circuit structure", Proc. IWLS '06, pp. 1522. PDF
 A. Mishchenko and R. K. Brayton, "Verification after synthesis", Proc. IWLS '06, pp. 263267. PDF
FPGA
 A. Mishchenko, S. Chatterjee, and R. Brayton, "Improvements to technology mapping for LUTbased FPGAs", Proc. FPGA '06, pp. 4149. PDF
Technical reports
 A. Mishchenko, S. Chatterjee, R. Brayton, and P. Pan, "Integrating logic synthesis, technology mapping, and retiming", ERL Technical Report, EECS Dept., UC Berkeley, April 2006. PDF
 G. Wang, A. Mishchenko, R. Brayton, and A. SangiovanniVincentelli, "Sequential synthesis with coBuchi specifications", ERL Technical Report, EECS Dept., UC Berkeley, April 2006. PDF
2005
Journals
 S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", IEEE Trans. CAD, Vol. 25(12), December 2006, pp. 28942903. PDF
 A. Mishchenko, J. S. Zhang, S. Sinha, J. R. Burch, R. Brayton, and M. ChrzanowskaJeske, "Using simulation and satisfiability to compute flexibilities in Boolean networks", IEEE Trans. CAD, Vol. 25(5), May 2006, pp. 743755. PDF (Best paper award.)
 A. Mishchenko and R. Brayton, "A theory of nondeterministic networks", IEEE Trans. CAD, Vol. 25(6), June 2006, pp. 977999. PDF
 J. S. Zhang, M. ChrzanowskaJeske, A. Mishchenko, and J. R. Burch, "Linear cofactor relationships in Boolean functions", IEEE Trans. CAD, Vol. 25(6), June 2006, pp. 10111023. PDF
 S. Nagayama, A. Mishchenko, T. Sasao, and J. T. Butler, "Exact and heuristic minimization of the average path length in decision diagrams", Journal of MultipleValued Logic and Soft Computing, 2005, Vol. 11, Num. 56, pp. 437465. PDF
ICCAD
 S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", Proc. ICCAD '05, pp. 519526. PDF
IWLS
 S. Chatterjee, A. Mishchenko, R. Brayton, X. Wang, and T. Kam, "Reducing structural bias in technology mapping", Proc. IWLS '05, pp. 375382. PDF
 A. Mishchenko, S. Chatterjee, R. Brayton, and M. Ciesielski, "An integrated technology mapping environment", Proc. IWLS '05, pp. 383390. PDF
 A. Mishchenko, S. Chatterjee, J.H. Jiang, and R. Brayton, "Integrating logic synthesis, technology mapping, and retiming", Proc. IWLS '05, pp. 177181. PDF
 J. Zhang, S. Sinha, A. Mishchenko, R. Brayton, and M. ChrzanowskaJeske, "Simulation and satisfiability in logic synthesis", Proc. IWLS '05, pp. 161168. PDF
ISCAS
 M. ChrzanowskaJeske and A. Mishchenko, "Synthesis for regularity using decision diagrams", Proc. International Symposium on Circuits and Systems (ISCAS '05), pp. 47214724. PDF
DATE
 A. Mishchenko and R. Brayton, "SATbased complete don'tcare computation for network optimization", Proc. DATE '05, pp. 418423. PDF
 A. Mishchenko, R. Brayton, R. Jiang, T. Villa, and N. Yevtushenko, "Efficient solution of language equations using partitioned representations", Proc. DATE '05, pp. 412417. PDF
ASPDAC
 J. S. Zhang, M. ChrzanowskaJeske, A. Mishchenko, and J. R. Burch, "Detecting supportreducing bound sets using twocofactor symmetries". Proc. ASPDAC '05, pp. 266271. PDF
Technical reports
 A. Mishchenko, S. Chatterjee, R. Jiang, and R. K. Brayton, "FRAIGs: A unifying representation for logic synthesis and verification". ERL Technical Report, EECS Dept., UC Berkeley, March 2005. PDF
 A. Mishchenko, S. Chatterjee, R. Brayton, X. Wang, and T. Kam, "Technology mapping with Boolean matching, supergates and choices". ERL Technical Report, EECS Dept., UC Berkeley, March 2005. PDF
2004
ICCAD
 J.H. R. Jiang, A. Mishchenko, and R. K. Brayton "On breakable cyclic definitions", Proc. ICCAD '04, pp. 411418. PDF
IWLS
 M. ChrzanowskaJeske, A. Mishchenko, J. S. Zhang, and M. Perkowski, "Logic synthesis for layout regularity using decision diagrams", Proc. IWLS '04, pp. 149154. PDF
 A. Mishchenko and R. K. Brayton, "SATbased complete don'tcare computation for network optimization", Proc. IWLS '04, pp. 353360. PDF
 A. Mishchenko, R. K. Brayton, J.H. R. Jiang, T. Villa, and N. Yevtushenko, "Efficient solution of language equations using partitioned representations", Proc. IWLS '04, pp. 401408. (See DATE '05)
 N. Yevtushenko, T. Villa, R. K. Brayton, A. Mishchenko, and A. L. SangiovanniVincentelli, "Composition operators in language equations", Proc. IWLS '04, pp. 409415. PDF
 J. S. Zhang, M. ChrzanowskaJeske, A. Mishchenko, and J. R. Burch, "Fast computation of generalized symmetries in Boolean functions", Proc. IWLS '04, pp. 424430. PDF
 J.H. R. Jiang, A. Mishchenko, and R. K. Brayton, "On breakable cyclic definitions", Proc. IWLS '04, pp. 454461. (See ICCAD '04)
2003
Journals
 A. Mishchenko, "Fast computation of symmetries in Boolean functions", IEEE Trans. CAD, Vol. 22(11), November 2003, pp.15881593. PDF
 X. Song, W. N. N. Hung, A. Mishchenko, M. ChrzanowskaJeske, A. Kennings, and A. Coppola, "Boardlevel multiterminal net assignment for the partial crossbar architecture", IEEE Trans. VLSI, Vol. 11 (3), June 2003, pp. 511514. PDF
ICCAD
 A. Mishchenko and R. K. Brayton, "A theory of nondeterministic networks", Proc. ICCAD '03, pp. 709717. PDF
DAC
 A. Mishchenko, X. Wang, and T. Kam, "A new enhanced constructive decomposition and mapping algorithm", Proc. DAC '03, pp. 143148. PDF
 A. Mishchenko and T. Sasao, "Largescale SOP minimization using decomposition and functional properties", Proc. DAC '03, pp. 149154. PDF
DATE
 J.H. R. Jiang, A. Mishchenko, and R. K. Brayton, "Reducing multivalued algebraic operations to binary", Proc. DATE '03, pp. 752757. PDF
IWLS
 S. Nagayama, A. Mishchenko, T. Sasao, and J. Butler, "Minimization of average path length in BDDs by variable reordering", Proc. IWLS '03, pp. 207213. PDF
 A. Mishchenko, R. Brayton, and T. Sasao, "Exploring multivalued minimization using binary methods", Proc. IWLS '03, pp. 278285. PDF
 R. K. Brayton and A. Mishchenko, "A theory of nondeterministic networks", Proc. IWLS '03, pp. 286293. (See ICCAD '03)
Technical reports
 J. Cortadella, M. Kishinevsky, and A. Mishchenko, "Restructuring multilevel networks by using function approximations", Technical report, March 2003. PDF
2002
Journals
 M. ChrzanowskaJeske, A. Mishchenko, and M. Perkowski, "Generalized inclusive forms: New canonical ReedMuller forms including minimum ESOPs", VLSI Design Journal, Vol. 14(1), January 2002, pp. 1321.
ICCAD
 A. Mishchenko and R. K. Brayton, "Simplification of nondeterministic multivalued networks", Proc. ICCAD '02, pp. 557562. PDF
 S. Sinha, A. Mishchenko, and R. K. Brayton, "Topologically constrained logic synthesis", Proc. ICCAD '02, pp. 679686. PDF
Lake Biwa Workshop
 A. Mishchenko and T. Sasao, "Logic synthesis of LUT cascades with limited rails: A direct implementation of multioutput functions", Proc. Lake Biwa Workshop '02. PDF
GLSVLSI
 X. Song, W. N. N. Hung, A. Mishchenko, M. ChrzanowskaJeske, A. J. Coppola, and A. A. Kennings, "Boardlevel multiterminal net assignment", Proc. ACM Great Lakes Symposium on VLSI '02, pp. 130135. PDF
ISMVL
 R. K. Brayton, M. Gao, J.H. R. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S. Sinha, and T. Villa, "Optimization of multivalued multilevel networks", Proc. ISMVL '02: 168177. PDF
IWLS
 A. Mishchenko and T. Sasao, "Encoding of Boolean functions and its application to LUT cascade synthesis", Proc. IWLS '02, pp. 115120. PDF
 S. Sinha, A. Mishchenko, and R. K. Brayton. "Topologically constrained logic synthesis", Proc. IWLS '02, pp. 1320. (See ICCAD '02)
 A. Mishchenko and R. K. Brayton, "A Boolean paradigm in multivalued logic synthesis", Proc. IWLS '02, pp. 173177. PDF
 A. Mishchenko and M. A. Perkowski, "Logic synthesis of reversible wave cascades", Proc. IWLS '02, pp. 197202. PDF
 A. Mishchenko and R. K. Brayton, "Simplification of nondeterministic multivalued networks", Proc. IWLS '02, pp. 333338. (See ICCAD '02)
 J.H. R. Jiang, A. Mishchenko, and R. K. Brayton, "Reducing multivalued algebraic operations to binary", Proc. IWLS '02, pp. 339344. (See DATE '03)
5th Intl Workshop on Boolean Problems, September 1920, 2002, Freiberg (Sachsen), Germany
 M. Perkowski and A. Mishchenko, "Logic synthesis for regular layout using satisfiability", Proc. Intl Workshop on Boolean Problems '02. PDF
 A. Mishchenko and R. Brayton, "A theory of nondeterministic networks", Proc. Intl Workshop on Boolean Problems '02.
Technical reports
 A. Mishchenko and R. K. Brayton, "Higherorder flexibilities in multivalued networks", ERL Technical Report, EECS Dept., UC Berkeley, May 2002. PDF
2001
DAC
 A. Mishchenko, B. Steinbach, and M. A. Perkowski, "An algorithm for bidecomposition of logic functions", Proc. DAC '01, pp. 103108. PDF
Fifth Intl Workshop on Applications of the Reed Muller Expansion in Circuit Design, Starkville, Mississippi, August 1011, 2001
 A. Mishchenko and M. Perkowski, "Fast heuristic minimization of exclusivesumsofproducts", Proc. ReedMuller Workshop '01, pp. 242250. PDF
 B. Steinbach and A. Mishchenko, "SNF: A special normal form for ESOPs", Proc. ReedMuller Workshop '01, pp. 6681. PDF
IWLS
 A. Mishchenko, B. Steinbach, and M. Perkowski, "Bidecomposition of multivalued relations", Proc. IWLS '01, pp. 3540. PDF
 J. Jacob and A. Mishchenko, "Unate decomposition of Boolean functions", Proc. IWLS '01, pp. 6671. PDF
 M. Perkowski, P. Kerntopf, A. Buller, M. ChrzanowskaJeske, A. Mishchenko, X. Song, A. AlRabadi, L. Jozwiak, A. Coppola, and B. Massey, "Regularity and symmetry as a base for efficient realization of reversible logic circuits", Proc. IWLS '01, pp. 9095.
Euromicro Symposium on Digital Systems Design, 46 September, 2001
 M. A. Perkowski, M. ChrzanowskaJeske, A. Mishchenko, X. Song, A. AlRabadi, B. Massey, P. Kerntopf, A. Buller, L. Jozwiak, and A. J. Coppola, "Regular realization of symmetric functions using reversible logic", Proc. Euromicro Symposium on Digital Systems Design '01, pp. 245253.
Technical reports
 A. Mishchenko, "An experimental evaluation of algorithms for computation of internal don'tcares in Boolean networks", Technical report, Portland State University, September 2001. PDF
 A. Mishchenko, "An introduction to zerosuppressed binary decision diagrams", Technical report, Portland State University, June 2001. PDF
 A. Mishchenko, "An approach to disjointsupport decomposition of logic functions", Technical report, Portland State University, February 2001. PDF
2000
 A. Mishchenko, C. Files, M. Perkowski, B. Steinbach, and Ch. Dorotska, "Implicit algorithms for multivalued input support manipulation", Proc. 4th Intl. Workshop on Boolean Problems, September 2000, Freiberg, Germany. PDF
 A. Mishchenko, "Implicit representation of discrete objects", Proc. 3d Oregon Symposium on Logic, Design, and Learning (LDL '00), May 22, 2000, Porland, Oregon.
 A. Mishchenko, "An efficient implementation of L language data processing algorithms", Proc. 2d International Conference UKRPROG '00 (May 2326, 2000), Kiev, Ukraine. Published in the special issue of the journal "Problemy Programirovaniya" (Problems in Programming), #12, 2000, pp. 335344.
1999
 M. A. Perkowski, R. Malvi, S. Grygiel, M. Burns, and A. Mishchenko, "Graph coloring algorithms for fast evaluation of Curtis decompositions", Proc. DAC '99, pp. 225230.
 M. A. Perkowski, A. Mishchenko, and A. N. Chebotarev, "Evolvable hardware or learning hardware? Induction of state machines from temporal logic constraints", Proc. First NASA/DoD Workshop on Evolvable Hardware '99, pp. 129138.
 N. Venkataramaiah, K. Dill, D. Hall, M. A. Perkowski, A. Mishchenko, and U. Kalay, "Highly testable finite state machines based on EXOR logic", Proc. 7th IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM '99), Victoria, B.C., Canada, August 2325, 1999, pp. 440443.
 M. ChrzanowskaJeske, A. Mishchenko, and M. Perkowski, "A family of canonical AND/EXOR forms that includes exact minimum ESOPs", Proc. Fourth Intl Workshop on Applications of the Reed Muller Expansion in Circuit Design, University of Victoria, Victoria B.C., Canada, August 2021, 1999, pp. 115.
 A. Mishchenko and M. A. Perkowski, "TRACE: A visual software system to explore properties of ReedMuller movement functions", Proc. Fourth Intl Workshop on Applications of the Reed Muller Expansion in Circuit Design, University of Victoria, Victoria B.C., Canada, August 2021, 1999, pp. 265271.