BVSRC

Berkeley Verification and Synthesis Research Center




BVSRC supports research in new methods for logic synthesis and formal verification combined with their efficient implementation as embodied in the system, ABC. We seek industrial partners who are interested in furthering research in these areas and experimenting with augmenting their design flows with new technologies, as well as in sharing their industrial experiences, new problems and design examples with university researchers. Our research exploits the synergy between synthesis and verification, recognizing that these areas share many algorithms; by focusing on the efficiency and scalability of the implementations of these common algorithms, significant advances can be achieved in both areas. Emphasis is placed on sequential designs and the scalability of the algorithms in this context. With a modest investment, center membership provides access to faculty and graduate students for defining research initiatives, consultation on special problems, aid in integrating design flows, and early access to research and implementations. The critical-mass combination of UC Berkeley researchers, government funding agencies, and a variety of companies in their respective areas opens up the possibility for significant advances. For membership information send email to:

bvsrc[at]eecs[dot]berkeley[dot]edu